用两片74LS148计划16-4线优先编码器
例1:试用两片74LS148计划一个16-4线优先编码器。容许附加必要的门电路。
解:依据优先编码器的逻辑功用,列出16-4线优先编码器的逻辑功用表如表1。~
为编码输入端,其间
的优先级最高,
的优先级最低。
~
为编码输出端。输入输出均为低电平有用。
表1 16-4线优先编码器逻辑功用表
输入 | 输出 | ||||||||||||||||||
A0 | A1 | A2 | A3 | A4 | A5 | A6 | A7 | A8 | A9 | A十 | A11 | A12 | A13 | A14 | A15 | Z3 | Z2 | Z1 | Z0 |
× | × | × | × | × | × | × | × | × | × | × | × | × | × | × | 0 | 0 | 0 | 0 | 0 |
× | × | × | × | × | × | × | × | × | × | × | × | × | × | 0 | 1 | 0 | 0 | 0 | 1 |
× | × | × | × | × | × | × | × | × | × | × | × | × | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
× | × | × | × | × | × | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
× | × | × | × | × | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
× | × | × | × | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
× | × | × | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
× | × | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
× | × | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
× | × | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
× | × | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
× | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
× | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
× | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
× | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
从表1中还能够看出,用多个优先编码器拓宽成别的多输入的优先编码器时,依据优先编码器的特征,构成的拓宽电路中,一贯只需一个编码器作业。优先级高的输入地址的编码器(地址的优先编码器为编码器Ⅰ,用74LS148(Ⅰ)标明)接在前面,优先级低的输入地址的编码器(地址的优先编码器为编码器Ⅱ,用72LS148(Ⅱ)标明)接在后边。且编码器按联接次第顺次开端作业(即74LS148(Ⅰ)先作业,72LS148(Ⅱ)后作业),当后边的编码器作业时,前面的编码器处于作业但没输入的状况。最前面的编码器一贯处于作业状况(将输入端接地)。
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